Method of determining event based energy weights for digital power estimation

ABSTRACT

A method for determining event based energy weights for digital power estimation includes obtaining a reference energy value corresponding to a power consumed by at least a portion of an integrated circuit (IC) device during operation. The method includes determining and selecting a subset of signals from a set of all signals within the IC that correlates to energy use within the IC. The method includes determining an activity factor of each signal in the subset by monitoring each signal while simulating execution of a particular set of instructions. The method includes determining a weight factor or at least an approximation of a weight factor for each signal in the subset by solving within a predetermined accuracy, a multivariable equation in which the reference energy value equals a weighted sum of the activity of the signals of the selected subset multiplied by their respective weight factors.

BACKGROUND

1. Technical Field

This disclosure relates to power usage estimation and, moreparticularly, to power usage estimation in a microprocessor usingdigital techniques.

2. Description of the Related Art

Many modern processors are capable of consuming a great deal of powerand in so doing may generate a significant amount of heat. If leftunchecked, this heat could cause catastrophic damage to the processor.Thus, power management systems have been developed to limit the powerthe processor consumes and thus the heat generated. In many powermanagement systems, the thermal design power (TDP) for the whole chip iscommonly the primary metric that is used to control power and ensurethermal limits are not exceeded. Typically, if the thermal limits arebeing reached, or the thermal power reaches a particular threshold, thepower management system may throttle the processor by reducingperformance. Conversely, if power consumption can be accurately measuredwhile running a given application, and the power used is less than theTDP capability of the platform, performance may be increased by allowingthe processor to consume the available headroom in the TDP by increasingthe operating voltage, the operating frequency or both. However, thecapabilities of conventional thermal measurement mechanisms have lessthan acceptable granularity and repeatability in many cases. Inaddition, conventional analog power measurement typically requirescomplex analog-to-digital converters and associated circuitry.

SUMMARY

Various embodiments of a method for determining event based energyweights for digital power estimation are disclosed. Estimating power onan integrated circuit device using digital techniques may requiregranularity and precision. Accordingly, power monitors have beendeveloped that monitor a set of signals for specific activity. Each suchsignal may correlate to a particular amount of the power consumed by theintegrated circuit device. This correlation may be referred to as theweight factor of a particular signal. Thus, for the power monitor to beable to accurately estimate the power consumed by the integrated circuitdevice or any portion thereof, the power monitor uses an appropriatesubset of signals to monitor, and the respective weight factor for eachsignal.

In one embodiment, the method includes obtaining a reference energyvalue corresponding to a power consumed by at least a portion of anintegrated circuit device during operation. The method may also includedetermining and selecting a subset of signals from a set of all signalswithin the integrated circuit device that correlate to energy use withinthe integrated circuit device. The method also includes determining anactivity factor of each signal in the selected subset of signals bymonitoring each signal while simulating execution of a particular set ofinstructions, such as a power test program, for example. The method mayfurther include determining a weight factor or at least an approximationof a weight factor for each signal in the selected subset of signalsbased on the energy value, the activity factors, and the respectiveweight factors. For example, the weight factors may be found by solvingwithin a predetermined accuracy percentage, a multivariable equation inwhich the reference energy value equals a weighted sum of the signals ofthe selected subset of signals multiplied by their respective weightfactors.

In one specific implementation, the method includes estimating the powerconsumed by at least a portion of an integrated circuit device byrunning a gate level simulation of a register transfer level (RTL)design of the integrated circuit device executing the particular set ofinstructions.

In another specific implementation, the method includes measuring thepower consumed by at least a portion of an integrated circuit device bycausing the integrated circuit device to execute the particular set ofinstructions and directly measuring the power consumed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of one embodiment of a processing node havingprocessor cores with digital power monitors.

FIG. 2 is a flow diagram depicting one embodiment of a method fordetermining the weight factors to apply to each signal during powermonitoring and estimation.

FIG. 3 is a flow diagram depicting another embodiment of a method fordetermining the weight factors to apply to each signal during powermonitoring and estimation.

FIG. 4 is a block diagram of one embodiment of a system for use indetermining the weight factors to apply to each signal during powermonitoring and estimation.

Specific embodiments are shown by way of example in the drawings andwill herein be described in detail. It should be understood, however,that the drawings and detailed description are not intended to limit theclaims to the particular embodiments disclosed, even where only a singleembodiment is described with respect to a particular feature. On thecontrary, the intention is to cover all modifications, equivalents andalternatives that would be apparent to a person skilled in the arthaving the benefit of this disclosure. Examples of features provided inthe disclosure are intended to be illustrative rather than restrictiveunless stated otherwise.

As used throughout this application, the word “may” is used in apermissive sense (i.e., meaning having the potential to), rather thanthe mandatory sense (i.e., meaning must). Similarly, the words“include,” “including,” and “includes” mean including, but not limitedto.

Various units, circuits, or other components may be described as“configured to” perform a task or tasks. In such contexts, “configuredto” is a broad recitation of structure generally meaning “havingcircuitry that” performs the task or tasks during operation. As such,the unit/circuit/component can be configured to perform the task evenwhen the unit/circuit/component is not currently on. In general, thecircuitry that forms the structure corresponding to “configured to” mayinclude hardware circuits. Similarly, various units/circuits/componentsmay be described as performing a task or tasks, for convenience in thedescription. Such descriptions should be interpreted as including thephrase “configured to.” Reciting a unit/circuit/component that isconfigured to perform one or more tasks is expressly intended not toinvoke 35 U.S.C. §112, paragraph six, interpretation for thatunit/circuit/component.

DETAILED DESCRIPTION

Turning now to FIG. 1, a simplified block diagram of one embodiment of aprocessing node is shown. In the illustrated embodiment, the processingnode 12 includes processor cores 15A-15B coupled to a node controller20. In one embodiment, node 12 may be a single integrated circuit chipcomprising the circuitry shown therein in FIG. 1. That is, node 12 maybe a chip multiprocessor (CMP). Other embodiments may implement the node12 as two or more separate integrated circuits, as desired. Any level ofintegration or discrete components may be used. It is noted thatcomponents having a number and a letter as a reference designator may bereferred to by the number only where appropriate.

It is also noted that, a processing node such as node 12 may include anynumber of processor cores, in various embodiments. It is further notedthat processor node 12 may include many other components that have beenomitted here for simplicity. For example, in various embodimentsprocessing node 12 may include an integral memory controller and variouscommunication interfaces for communicating with other nodes, and I/Odevices.

In one embodiment, node controller 20 may include variousinterconnection circuits (not shown) for interconnecting processor cores15A and 15B to each other, to other nodes, and to a system memory (notshown). As shown, the node controller 20 includes a power manager 21that may be configured to control the amount of power consumed by eachprocessor core 15 and therefore, the amount of heat generated. The powermanager 21 may be configured to control the operating frequency for eachcore and/or the power supply voltages for the node using the voltageidentifier (VID) signals provided to the voltage regulator(s). In oneembodiment, the maximum and minimum operating frequencies for the nodeand the maximum and minimum power supply voltages for the node may beprovided via fuses that are blown during manufacture. In addition, asdescribed further below, the power manager 21 may be configured tocontrol the power consumed by each core based upon power estimatesprovided by the power monitors 17A and 17B within each of processorcores 15A and 15B, respectively.

Generally, a processor core (e.g., 15A-15B) may include circuitry thatis designed to execute instructions defined in a given instruction setarchitecture. That is, the processor core circuitry may be configured tofetch, decode, execute, and store results of the instructions defined inthe instruction set architecture. For example, in one embodiment,processor cores 15A-15B may implement the x86 architecture. Theprocessor cores 15A-15B may comprise any desired configurations,including superpipelined, superscalar, or combinations thereof. Otherconfigurations may include scalar, pipelined, non-pipelined, etc.Various embodiments may employ out of order speculative execution or inorder execution. The processor core may include microcoding for one ormore instructions or other functions, in combination with any of theabove constructions. Various embodiments may implement a variety ofother design features such as caches (e.g., L1 and L2 caches), TLBs,etc. These various design features and microarchitectural blocksdescribed above are represented in FIG. 1 as functional blocks 16A and16B of processor cores 15A and 15B, respectively.

In the illustrated embodiment, processor core 15A includes a powermonitor 17A, which includes one or more storages (e.g., reg. 19A), forexample. Likewise, processor core 15B includes a power monitor 17B,which also includes one or more storages (e.g., reg. 19B), for example.As described further below, the power monitors 17 may be configured tostore signal names and corresponding weight factor values. In variousembodiments, the signal names may be programmed into the power monitorseither during manufacturing, or using specialized test modes aftermanufacture. Similarly, for the weight factor values. As will bedescribed in greater detail below in conjunction with the description ofFIG. 2 and FIG. 3, in various embodiments, the signals may be selectedand their corresponding weight factors may be determined usingtechniques such as gate level simulation of a register transfer level(RTL) design of the IC, as well as direct monitoring of a representativeIC device. An exemplary system for performing the RTL simulation ordirectly measuring power from the IC is shown in FIG. 4.

In addition, using the signals and weight factors each power monitor 17may also be configured to estimate the total power consumed, as well asthe power consumed by individual portions of a respective processor core15 within which it is located using digital techniques. Moreparticularly, in one embodiment, each power monitor 17 may be configuredto monitor the activity factor or level of each signal that has beenprogrammed into it, and to multiply that activity factor by the weightfactor for that signal. The power monitor may, depending on how it isprogrammed, sum the resulting energy values for each monitored signal toobtain the total energy value for the IC. In another embodiment, eachpower monitor 17 may calculate the energy value for only specifiedportions of the IC. The power monitors 17 may then provide energyvalue(s) that correspond to the consumed power to the power manager 21.In response to the energy values provided by the power monitors 17, thepower manager 21 may increase or decrease the frequency of one or morecores, increase or decrease the operating voltages of the cores, orotherwise control the operational state of the cores in an effort tooptimize performance while staying within the thermal budget of theprocessing node 12.

FIG. 2 is a flow diagram describing a method for determining the weightfactors to apply to each signal during power monitoring and estimation.Referring collectively to FIG. 1 and FIG. 2, and beginning in block 201of FIG. 2, an energy value that corresponds to the power consumed by theIC under a predetermined set of conditions is obtained. For example, aset of instructions may be executed that may be designed to exerciseeither specific portions or as much of the IC as possible, as desired,thereby causing the IC to consume a great deal of power. This set ofinstructions is commonly referred to as a “power virus” program. In oneembodiment, a physical IC device may execute the instructions and thetotal power consumed may be measured directly on a test bench or otherplatform designed for that purpose. In another embodiment, a synthesistool may run a gate level simulation the RTL design of the IC while theIC design executes the set of instructions. In one particularimplementation the RTL design may include a resistance and capacitanceannotated netlist of the IC. The synthesis tool may then estimate thepower consumed by the IC device. In either case, the energy value thatcorresponds to the power consumed by the IC is used as a referenceenergy value or “gold standard.”

In another embodiment, it may be possible to measure the power consumedby individual portions of the IC. It is noted that the usingsuperposition, the total power consumed would be equal to the sum of thepower consumed by all the individual portions of the IC.

Once the reference energy value has been obtained, a candidate set (orsubset) of microarchitectural events and their corresponding signals maybe chosen from all of the signals in the IC or portion of interest ofthe IC (block 203). In one embodiment, the set of signals may beselected such that an activity level on a given signal is correlates toa particular energy use. For example, enable signals for major memoryarrays, or clock gating signals to flip-flops may be used.Alternatively, signals from a much higher level in the design may bechosen. More particularly, microarchitectural performance monitorsignals that may be used to characterize application performance andactivity on high level microarchitectural blocks may be used, forexample.

Once the signals have been chosen, an RTL gate level simulation may beperformed on the IC design and the activity factor of each of the chosensignals may be determined (block 205). The weight factor that will beapplied to each signal during actual power estimation on the IC may nowbe determined. More particularly, to calculate the weight factor foreach signal, a multivariable equation of ‘n’ signals (shown inequation 1) is set up and solved using any of a variety of techniques(block 207). The equation represents performing a weighted sum of events(activity factors)×weight factors. As such Equation 1 is as follows:

E _(m)Σ_(k=1) ^(n) W _(k) *A _(mk)  (1)

where E_(m) is the total energy value used to run a workload m and thatwas determined in block 201. The W_(k) is the weight factor of signal k,and A_(km) represents the activity factor for each signal k in workloadm. Thus, each signal will be assigned a corresponding weight factor, andthe sum of the sets should equal E_(m).

It is noted that depending on the number of signals and other factors,it may be difficult if not impossible to exactly solve the equation.However, using various optimization methods, the equation may be solvedsuch that a sufficient approximation may reached which provides weightfactors that yield an E_(m) that is close enough to within somepredetermined accuracy or percentage of the reference energy value(block 209).

When solving for the weight factors, as the number of signals increases,the problem complexity may become unwieldy. Accordingly, it may bepossible to reduce the complexity by constraining the system in someway. For example, there may be many replicated structures such asfunctional units in the design. When these are identified, equation 1may be modified such that W_(k)*A_(km) becomes W_(k)(A_(k1m)+A_(k2m) + .. . A _(kxm)), where each replicated structure k₁ . . . k₂ . . . k_(x)now shares the same weight factor W_(k), which may reduce the number ofweights for which to solve.

As mentioned above, linear superposition may be used to add up theenergy values of individual portions of the IC to obtain a total energy.Accordingly, in one embodiment, this principle may be used whencalculating the weight factors. For example, instead of calculating theweight factors for the whole IC, the weight factors may be calculatedfor individual blocks, as long as a reference energy value was obtainedfor those individual blocks.

If the accuracy is not good enough (i.e., it is not within apredetermined accuracy) (block 211), additional signals may be added tothe candidate set of signals (block 213), and the operation proceeds asdescribed above in block 205 through 211, where an RTL simulation isperformed to determine the activity factors for the added signals, andthe weight factors are found through solving Equation 1.

Referring back to block 211, if the accuracy of the weight factors isclose enough, the number of signals may be checked (block 215). Moreparticularly, it is possible that during one or more early passesthrough the process, the accuracy was well within the predeterminedaccuracy threshold, but the number of signals may be too high. In suchcases, it may be possible to reduce the number of signals while stillmaintaining an acceptable accuracy. Accordingly, if the number ofsignals is too high, the number of signals may be reduced one signal ata time (block 219). In various embodiments, it may be possible to useany of a variety of computer aided design optimization methods. Forexample, there are genetic algorithms, simulated annealing algorithms,and signal group removal, and the like. The particular method of signalremoval is not germane to this disclosure. The process then proceeds asdescribed above in block 209, in which Equation 1 is solved again forthe new number of signals. Referring back to block 215, if the number ofsignals is within a predetermined number, then the signal selectionprocess is complete.

Once the process is completed, the signal list and corresponding weightsmay be used in the physical IC. More particularly, in one embodiment, asmentioned above, the signal names and thus the corresponding signalpaths may be hardwired into the IC design and manufactured so that thepower monitor 17 may always monitor those signals. In anotherembodiment, the signals may be programmed into reg. 19 and used byfirmware within the power monitor 17. The weight factors may beprogrammed into the reg 19 of each power monitor 17.

As mentioned above, rather than solve equation 1 to determine eachweight factor, it is possible to experimentally determine the weightfactors on the physical IC device. Turning to FIG. 3, a flow diagramdescribing another method for determining the weight factors to apply toeach signal during power monitoring and estimation is shown. Beginningin block 301, once the signals to be monitored are hardwired orprogrammed into the power monitor 17, the weight factor values may beprogrammed into the reg 19 of the power monitor 17. It is noted that thesignals to be monitored may be determined as described above inconjunction with the description of FIG. 2, for example. The set ofinstructions that exercise the IC may be executed by the IC, and thepower monitor 17 may estimate an energy value that corresponds to thepower consumed. In one embodiment, an application program may beexecuted to extract the energy information from the node controller 20.

The estimated energy value may be compared with the reference energyvalue that was determined as described above. If the estimated energyvalue is not within a predetermined accuracy percentage, or otherwise isnot accurate enough (block 303), operation proceeds as described inblock 301, in which new weight factor values may be programmed into thepower monitor 17. This process may be iterated as many times asnecessary to obtain weight factor values that yield an estimated energyvalue that has the requisite precision when compared to the referenceenergy value. Once the estimated energy value meets the requiredprecision, the process is complete (block 305). Those weight values maythen be used during operation of the IC for digital power monitoring.

As mentioned above, an exemplary system is shown on which thedetermining of the weight factors may be performed using eithersimulations of the IC design or the physical IC device itself Referringto FIG. 4, a block diagram of one embodiment of a system for use indetermining the weight factors is shown. The system 400 includes aprocessing unit 401 that is coupled to a storage 407. The processingunit 401 is also coupled to an IC device 421. As shown, the storage 407may include data files such as IC device net list 411 and signal andweight list 415, and application and test programs 413.

In one embodiment, system 400 may be a test platform used to designand/or test IC devices such as IC device 421. More particularly,processing unit 401 may include one or more processors that may beconfigured to execute application and test programs 413. Processing unit401 may also include various peripheral and I/O support hardware (notshown) for communication with IC device 421. In addition, processingunit 401 may include memory controller hardware for controlling accessesto storage 407, as well as any internal system memory that may be partof processing unit 401.

As described above, an IC design tool such as a synthesis tool may beused to run simulations. Accordingly, IC device net list 411 may berepresentative of an RTL net list of an IC device such as the IC device421. In addition, application and test programs 413 may include ICdesign software including synthesis and layout tools, as well as testprograms that exercise the IC device 421 during power monitoring etc. Inaddition, application and test programs 413 may also include specifictest programs to access and exercise the IC device 421, and to provideresults back to processing unit 401. In one embodiment, the signal andweight list 415 may be a listing of the signals that will be monitoredby power monitors 17 along with the corresponding weight factors.

The storage 407 may be representative of any type of computer readablememory medium. For example in various embodiments, storage 407 mayinclude any memory medium on which computer programs according tovarious embodiments may be stored. The term “memory medium” may includean installation medium, e.g., a CD-ROM, or floppy disks 160, a computersystem memory such as DRAM, SRAM, EDO DRAM, SDRAM, DDR SDRAM, RambusRAM, etc., or a non-volatile memory such as a magnetic media, e.g., ahard drive, or optical storage.

In various embodiments, the methods described above may be performedeither wholly or in part on the system 400, as desired. Moreparticularly, the method described in FIG. 2 may be performed usingsystem 400. For example, the processing unit 401 may be used to executeapplication and test programs such as a synthesis engine to perform thegate level simulation of the IC design included in the IC device netlist411. The simulation may include the IC design executing anotherapplication and test program to exercise the simulation of the IC designso that signal activity may be recorded. Furthermore, an additionalapplication and test program may be executed by processing unit 401 tocalculate the weight factors.

In addition, the system 400 may be used as an IC test platform to testthe physical IC device 421, as described above in conjunction with thedescription of FIG. 3. In such an embodiment, the processing unit 401may execute a test program that may access IC device 421 to iterativelyprogram weight factors into the power monitors 17 and to load the set ofinstructions that exercise the IC device 421.

In one embodiment, a specialized application and test program may causethe entire process shown in FIG. 2 to execute automatically. Moreparticularly, a test program may automatically load the net list 411,cause the synthesis tool to run the simulation of the netlist 411, whilea test program is executed by the simulated IC. The specialized testprogram may extract timing and activity information from the synthesistool output to automatically select the candidate signals. In addition,the test program may then set up and solve equation 1 above for theweight factors, and then if necessary, iteratively add and or removesignals and recheck the accuracy. The test program may also output thesignal and weight list 415 at the completion of the process.

Although the embodiments above have been described in considerabledetail, numerous variations and modifications will become apparent tothose skilled in the art once the above disclosure is fully appreciated.It is intended that the following claims be interpreted to embrace allsuch variations and modifications.

1. A method comprising: obtaining an energy value corresponding to apower consumed by at least a portion of an integrated circuit deviceduring operation; selecting a subset of signals from a set of allsignals within the integrated circuit device that correlates to energyuse within the integrated circuit device; determining an activity factorof each signal in the selected subset of signals by monitoring eachsignal in the selected subset of signals while simulating execution of aparticular set of instructions; and determining at least anapproximation of a weight factor for each signal in the selected subsetof signals based on the energy value, the activity factors and therespective weight factors.
 2. The method as recited in claim 1, furthercomprising estimating the power consumed by the at least a portion of anintegrated circuit device by running a gate level simulation of aregister transfer level (RTL) design of the integrated circuit deviceexecuting the particular set of instructions.
 3. The method as recitedin claim 2, wherein the RTL design includes a netlist that is annotatedwith resistance and capacitance values.
 4. The method as recited inclaim 1, further comprising measuring the power consumed by the at leasta portion of an integrated circuit device by causing the integratedcircuit device to execute the particular set of instructions anddirectly measuring the power consumed.
 5. The method as recited in claim1, wherein the activity factor for a given signal corresponds to anumber of times the given signal transitions from one logic value toanother logic value during a particular period of the simulation.
 6. Themethod as recited in claim 1, further comprising generating a list ofthe selected subset of signals and their respective corresponding weightfactors.
 7. The method as recited in claim 1, further comprisingprogramming the weight factors into a power monitor unit of theintegrated circuit device and generating an estimated energy value ofrespective portions of the integrated circuit device during operation.8. The method as recited in claim 1, further comprising determining theweight factor for each signal by solving within a predeterminedpercentage, a multivariable equation in which the energy value equals aweighted sum of the activity factor of the signals of the selectedsubset of signals multiplied by their respective weight factor.
 9. Amethod comprising: obtaining an energy value by measuring a powerconsumed by at least a portion of an integrated circuit device duringoperation; selecting a subset of signals from a set of all signals thatcorrelate to energy use within the integrated circuit device;determining an activity factor of each signal in the selected subset ofsignals by monitoring each signal in the selected subset of signalswhile simulating execution of a particular set of instructions; anddetermining a final weight factor for each signal in the selected subsetof signals by iteratively programming the integrated circuit device witha new weight factor value for at least some of the signals in theselected subset of signals and re-executing the particular set ofinstructions using the new weight factor values until an estimatedenergy value is within a predetermined percentage of the energy value.10. The method as recited in claim 9, wherein the activity factor for agiven signal corresponds to a number of times the given signaltransitions from one logic value another logic value during thesimulation.
 11. The method as recited in claim 9, further comprisinggenerating a list of the selected subset of signals and their respectivecorresponding weight factors.
 12. The method as recited in claim 9,further comprising programming the final weight factors into a powermonitor unit of the integrated circuit and generating an estimatedenergy value of respective portions of the integrated circuit deviceduring operation.
 13. A computer readable storage medium includingprogram instructions executable by a processor to obtain an energy valuecorresponding to a power consumed by at least a portion of an integratedcircuit device during operation; select a subset of signals from a setof all signals within the integrated circuit device that correlate toenergy use within the integrated circuit device; determine an activityfactor of each signal in the selected subset of signals by monitoringeach signal in the selected subset of signals while simulating executionof a particular set of instructions; and determine at least anapproximation of a weight factor for each signal in the selected subsetof signals based on the energy value, the activity factors, and therespective weight factors.
 14. The computer readable storage medium asrecited in claim 13, wherein the program instructions comprise a testprogram configured to automatically generate a list including theselected subset of signals and a corresponding respective weight factorfor each signal in the subset of signals.
 15. The computer readablestorage medium as recited in claim 14, wherein the test program isfurther configured to launch a synthesis tool to perform the simulationof a register transfer level (RTL) netlist of at least a portion of theintegrated circuit device while the integrated circuit device isexecuting the particular set of instructions.
 16. The computer readablestorage medium as recited in claim 15, wherein the test program isfurther configured to solve within a predetermined percentage, amultivariable equation in which the energy value equals a weighted sumof the activity factor of the signals of the selected subset of signalsmultiplied by their respective weight factor.
 17. The computer readablestorage medium as recited in claim 16, wherein the test program isfurther configured to iteratively add one or more signals to the subsetof signals, determine the activity factor of each added signal in theselected subset, and to solve the multivariable equation until asolution to the multivariable equation is within the predeterminedpercentage.
 18. The computer readable storage medium as recited in claim16, wherein the test program is further configured to iteratively removeone or more signals and solve the multivariable equation until a numberof signals from the selected subset of signals is less than apredetermined number.
 19. A system comprising: a processing unitconfigured to execute program instructions; a storage coupled to theprocessing unit and configured to store the program instructions;wherein, when executed, the program instructions are configured to:obtain an energy value corresponding to a power consumed by at least aportion of an integrated circuit device during operation; select asubset of signals from a set of all signals within the integratedcircuit device that correlate to energy use within the integratedcircuit device; determine an activity factor of each signal in theselected subset of signals by monitoring each signal in the selectedsubset of signals while simulating execution of a particular set ofinstructions; and determine at least an approximation of a weight factorfor each signal in the selected subset of signals based on the energyvalue, the activity factors, and the respective weight factors.
 20. Thesystem as recited in claim 19, wherein the program instructions comprisea test program configured to automatically generate a list including theselected subset of signals and a corresponding respective weight factorfor each signal in the selected subset of signals.
 21. The system asrecited in claim 20, wherein the test program is further configured tosolve within a predetermined percentage, a multivariable equation inwhich the energy value equals a weighted sum of the activity factor ofthe signals of the selected subset of signals multiplied by theirrespective weight factor.
 22. The system as recited in claim 21, whereinthe test program is further configured to iteratively add one or moresignals to the selected subset of signals, determine the activity factorof each added signal in the selected subset, and to solve themultivariable equation until a solution to the multivariable equation iswithin the predetermined percentage.